1. Technical Field
The present invention relates to simulation and test of circuits and, in particular, to analysis of simulation and test coverage. More particularly, the present invention provides simulation and test coverage information using digital signal processing transforms.
2. Description of Related Art
Today""s very large scale integration (VLSI) designs grow with exponential as the time to market continually constrains the time available to develop and test products. The most common design validation technique is simulation, where input vectors are applied to the design and the design is then checked for the desired functionality at its outputs. With combination circuits, it is easy to see that an exhaustive set of input stimulus consists of every possible combination of input signals.
When memory elements, such as latches and Arrays, are added to these designs, the logic is referred to as xe2x80x9csequential logic.xe2x80x9d The outputs of these circuits are a function of the inputs and the values in the memory elements. Therefore, one must consider every possible combination of input vectors and memory states to ensure an exhaustive set of input stimulus. An xe2x80x9cinput vectorxe2x80x9d is generally defined as an ordered grouping of all the input signals. However, an input vector may comprise a subset of the input signals. With designs having gates in the number of millions, it becomes impossible to exhaustively verify a design within a competitive time frame.
As a result, input vectors are typically chosen that excite particular behaviors. This technique is referred to as xe2x80x9cevent coverage.xe2x80x9d For example, if the design is a graphics accelerator, inputs that draw shapes may be chosen. Thus, the problem becomes one of determining input vectors, which ensure that properties of the design are maintained without explicitly understanding which input vectors exhibit these properties. In the example of a graphics accelerator, if a vertex queue has a fixed length, a property of the design may be that no combination of shapes would be drawn that results in an overflow of this queue. Since the input vector sequences that demonstrate this property are not evident, several thousand input vectors may be applied. Because some of the inputs would be logical xe2x80x9cdon""t caresxe2x80x9d for this particular property, it is often the case in testing a property that many redundant vectors are applied to the design making the process inefficient.
The increasing number of output states and the increasing number of input vectors needed to produce desired output states results in a cumbersome amount of data to store and analyze. The prior art provides compression for storage of the output states and comparison of the compressed data. However, the amount of data, even with compression, is still unwieldy and difficult to analyze.
Therefore, it would be advantageous to have improved method and apparatus for analyzing the coverage of simulation and test input vectors.
The present invention assigns a unique label for every unique cycle of data produced by simulation or testing. The labels are substituted for the signal evaluations producing a graph of labels over time. The present invention then generates a function, which represents the graph and the function is stored. Since the function is stored using a small amount of text, as opposed to thousands or millions of states, the labeling and function generation of the present invention results in a form of data compression. Furthermore, the present invention compares the functions to determine coverage information. For example, if two functions overlap, the coverage information may indicate that inputs are producing redundant results.